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ISCA
1997
IEEE
98views Hardware» more  ISCA 1997»
13 years 11 months ago
Memory-System Design Considerations for Dynamically-Scheduled Processors
Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvon...
LCTRTS
2007
Springer
14 years 1 months ago
Enabling compiler flow for embedded VLIW DSP processors with distributed register files
High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in desig...
Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Y...
ICCD
2006
IEEE
103views Hardware» more  ICCD 2006»
14 years 4 months ago
Reduce Register Files Leakage Through Discharging Cells
— We propose a low-leakage register file cell design based on the observation that the physical registers in a superscalar processor have very short life cycles. When a register...
Lingling Jin, Wei Wu, Jun Yang 0002, Chuanjun Zhan...
VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
14 years 7 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
ASPLOS
2004
ACM
14 years 17 days ago
Continual flow pipelines
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkar...