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DAC
2009
ACM
16 years 25 days ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
CODES
2007
IEEE
16 years 11 days ago
HW/SW co-design for Esterel processing
We present a co-synthesis approach that accelerates reactive software processing by moving the calculation of complex expressions into external combinational hardware. The startin...
Sascha Gädtke, Claus Traulsen, Reinhard von H...
ESTIMEDIA
2007
Springer
16 years 5 days ago
Leveraging Predicated Execution for Multimedia Processing
—Modern compression standards such as H.264, DivX, or VC-1 provide astonishing quality at the costs of steadily increasing processing requirements. Therefore, efficient solution...
Dietmar Ebner, Florian Brandner, Andreas Krall
ISSTA
2006
ACM
15 years 12 months ago
Towards supporting the architecture design process through evaluation of design alternatives
This paper addresses issues involved when an architect explore alternative designs including non-functional requirements; in our approach, non-functional requirements are expresse...
Lihua Xu, Scott A. Hendrickson, Eric Hettwer, Hada...
ICPPW
2002
IEEE
15 years 11 months ago
SNOW: Software Systems for Process Migration in High-Performance, Heterogeneous Distributed Environments
This paper reports our experiences on the Scalable Network Of Workstation (SNOW) project, which implements a novel methodology to support user-level process migration for traditio...
Kasidit Chanchio, Xian-He Sun