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MASCOTS
2004
15 years 15 days ago
Design and Implementation of a High Speed Microprocessor Simulator BurstScalar
This paper describes the design and implementation of our high speed simulator for out-of-order microprocessors named BurstScalar. The simulator is based on the wellknown SimpleSc...
Takashi Nakada, Hiroshi Nakashima
GLVLSI
2005
IEEE
152views VLSI» more  GLVLSI 2005»
15 years 4 months ago
A high speed and leakage-tolerant domino logic for high fan-in gates
Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose a new domino circuit for high fan-in ...
Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peirav...
79
Voted
ENTCS
2007
95views more  ENTCS 2007»
14 years 11 months ago
Rijndael for Sensor Networks: Is Speed the Main Issue?
We present an implementation of Rijndael for wireless sensor networks running on Eyes sensor nodes. In previous works, Rijndael has not been considered a suitable encryption algor...
Andrea Vitaletti, Gianni Palombizio
82
Voted
ASPDAC
2006
ACM
105views Hardware» more  ASPDAC 2006»
15 years 5 months ago
Speed binning aware design methodology to improve profit under parameter variations
—Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-...
Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saib...
HOTI
2005
IEEE
15 years 4 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu