867 search results - page 43 / 174 » The Design and Performance of a Conflict-Avoiding Cache |
100
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DAC
2008
ACM
16 years 24 days ago
2008
ACM
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
203
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GLVLSI
2011
IEEE
14 years 3 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
104
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ISCA
1997
IEEE
15 years 4 months ago
1997
IEEE
The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. D...
ICCAD
1999
IEEE
15 years 4 months ago
1999
IEEE
Minimizing power consumption is of paramount importance during the design of embedded (mobile computing) systems that come as systems-ona-chip, since interdependencies of design c...
133
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HPCA
2011
IEEE
14 years 3 months ago
2011
IEEE
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...