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» The Design and Performance of a Conflict-Avoiding Cache
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CLUSTER
2008
IEEE
15 years 6 months ago
High message rate, NIC-based atomics: Design and performance considerations
—Remote atomic memory operations are critical for achieving high-performance synchronization in tightly-coupled systems. Previous approaches to implementing atomic memory operati...
Keith D. Underwood, Michael Levenhagen, K. Scott H...
IEEEPACT
2009
IEEE
14 years 9 months ago
Core-Selectability in Chip Multiprocessors
Abstract--The centralized structures necessary for the extraction of instruction-level parallelism (ILP) are consuming progressively smaller portions of the total die area of chip ...
Hashem Hashemi Najaf-abadi, Niket Kumar Choudhary,...
CAL
2002
14 years 11 months ago
Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example
Embedded systems commonly execute one program for their lifetime. Designing embedded system architectures with configurable components, such that those components can be tuned to t...
Ann Gordon-Ross, Susan Cotterell, Frank Vahid
VLSID
2002
IEEE
114views VLSI» more  VLSID 2002»
15 years 4 months ago
Minimizing Energy Consumption for High-Performance Processing
Power consumption is becoming an increasingly important constraint in the design of microprocessors. This paper examines the use of multiple constrained processors running at lowe...
Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti
ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
15 years 5 months ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...