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» The Design and Performance of a Conflict-Avoiding Cache
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ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
15 years 1 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner
DAC
1998
ACM
16 years 23 days ago
Code Compression for Embedded Systems
Memory is one of the most restricted resources in many modern embedded systems. Code compression can provide substantial savings in terms of size. In a compressed code CPU, a cach...
Haris Lekatsas, Wayne Wolf
ICDCS
2007
IEEE
15 years 6 months ago
STEP: Sequentiality and Thrashing Detection Based Prefetching to Improve Performance of Networked Storage Servers
State-of-the-art networked storage servers are equipped with increasingly powerful computing capability and large DRAM memory as storage caches. However, their contribution to the...
Shuang Liang, Song Jiang, Xiaodong Zhang
ISLPED
2003
ACM
87views Hardware» more  ISLPED 2003»
15 years 5 months ago
On load latency in low-power caches
Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of nondeterminism in cache access latency. Due to this additional late...
Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Ir...
ISCA
2002
IEEE
82views Hardware» more  ISCA 2002»
15 years 4 months ago
Increasing Processor Performance by Implementing Deeper Pipelines
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
Eric Sprangle, Doug Carmean