4305 search results - page 98 / 861 » The Test of Time |
153
click to vote
ICST
2010
IEEE
15 years 4 months ago
2010
IEEE
—A random testing strategy can be effective at finding faults, but may leave some routines entirely untested if it never gets to call them on objects satisfying their preconditi...
162
click to vote
3DIC
2009
IEEE
16 years 25 days ago
2009
IEEE
—A high-sensitivity capacitive-coupling interface is presented for wireless wafer testing systems. The transmitter is a buffer that drives the transmitter pad, and the receiver c...
178
click to vote
DATE
2005
IEEE
15 years 11 months ago
2005
IEEE
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
158
click to vote
MTV
2005
IEEE
15 years 11 months ago
2005
IEEE
Semiconductor manufacturers aim at deliver new devices within shorter times in order to gain market shares. First silicon debug is an important issue in order to minimize the time...
149
click to vote
ITC
2002
IEEE
15 years 11 months ago
2002
IEEE
Conventional fault simulation techniques for FPGAs are very complicated and time consuming. The other alternative, FPGA fault emulation technique, is incomplete, and can be used o...