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» Time Management in the DoD High Level Architecture
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DFT
1999
IEEE
125views VLSI» more  DFT 1999»
15 years 2 months ago
Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures
The inherent redundancy and in-the-field reconfiguration capabilities of field programmable gate arrays (FPGAs) provide alternatives to integrated circuit redundancy-based fault r...
John Lach, William H. Mangione-Smith, Miodrag Potk...
COMPSAC
2002
IEEE
15 years 2 months ago
A Distributed Architecture for Cooperative and Adaptative Multimedia Applications
Previously, we developed a method and a distributed platform for the re-engineering of applications by adding cooperation. The goal was to supply a way of communication based on t...
Philippe Roose, Marc Dalmau, Franck Luthon
ISCA
2011
IEEE
269views Hardware» more  ISCA 2011»
14 years 1 months ago
Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security
High assurance systems used in avionics, medical implants, and cryptographic devices often rely on a small trusted base of hardware and software to manage the rest of the system. ...
Mohit Tiwari, Jason Oberg, Xun Li 0001, Jonathan V...
IFE
2010
161views more  IFE 2010»
14 years 8 months ago
Adaptive estimation and prediction of power and performance in high performance computing
Power consumption has become an increasingly important constraint in high-performancecomputing systems, shifting the focus from peak performance towards improving power efficiency...
Reza Zamani, Ahmad Afsahi
ISCAS
2006
IEEE
124views Hardware» more  ISCAS 2006»
15 years 3 months ago
Systematic design flow for dynamic data management in visual texture decoder of MPEG-4
Abstract— There is a clear trend of future embedded systems in moving toward wireless, multimedia, multi-functional and ubiquitous applications. This emerges new challenges in th...
Alexandros Bartzas, Miguel Peón Quiró...