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ISCA
2007
IEEE
145views Hardware» more  ISCA 2007»
15 years 6 months ago
Mechanisms for store-wait-free multiprocessors
Store misses cause significant delays in shared-memory multiprocessors because of limited store buffering and ordering constraints required for proper synchronization. Today, prog...
Thomas F. Wenisch, Anastassia Ailamaki, Babak Fals...
ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
15 years 6 months ago
Dynamic prediction of architectural vulnerability from microarchitectural state
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
Kristen R. Walcott, Greg Humphreys, Sudhanva Gurum...
ISCA
2007
IEEE
167views Hardware» more  ISCA 2007»
15 years 6 months ago
New cache designs for thwarting software cache-based side channel attacks
Software cache-based side channel attacks are a serious new class of threats for computers. Unlike physical side channel attacks that mostly target embedded cryptographic devices,...
Zhenghong Wang, Ruby B. Lee
ISCA
2007
IEEE
103views Hardware» more  ISCA 2007»
15 years 6 months ago
Ginger: control independence using tag rewriting
The negative performance impact of branch mis-predictions can be reduced by exploiting control independence (CI). When a branch mis-predicts, the wrong-path instructions up to the...
Andrew D. Hilton, Amir Roth
ISCA
2007
IEEE
106views Hardware» more  ISCA 2007»
15 years 6 months ago
Architectural implications of brick and mortar silicon manufacturing
We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, ...