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73
Voted
NIPS
2007
15 years 1 months ago
2007
We describe an analog-VLSI neural network for face recognition based on subspace methods. The system uses a dimensionality-reduction network whose coefficients can be either progr...
NIPS
2004
15 years 1 months ago
2004
An analog system-on-chip for kernel-based pattern classification and sequence estimation is presented. State transition probabilities conditioned on input data are generated by an...
NIPS
1996
15 years 1 months ago
1996
We describe the implementation of a hidden Markov model state decoding system, a component for a wordspotting speech recognition system. The key specification for this state decod...
103
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ISCAS
2007
IEEE
15 years 6 months ago
2007
IEEE
Abstract— This paper describes the first VLSI implementation of lattice reduction (LR) aided multi-antenna broadcast precoding with vector perturbation. The considered LR scheme...
106
click to vote
ISCAS
2007
IEEE
15 years 6 months ago
2007
IEEE
In this paper, an efficient VLSI architecture for a fast computation of the 2-D discrete wavelet transform (DWT) is proposed. The architecture employing a three-stage cascade in p...