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    OL
    2007
    68views more  OL 2007»
    An ILP based hierarchical global routing approach for VLSI ASIC design
    14 years 11 months ago
    An ILP based hierarchical global routing approach for VLSI ASIC design
    Download  orion.math.uwaterloo.ca
    Zhen Yang, Anthony Vannelli, Shawki Areibi
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    VLSID
    2007
    IEEE
    120views VLSI» more  VLSID 2007»
    VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition
    16 years 2 days ago
    VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition
    Download  www.utdallas.edu
    Chitranjan K. Singh, Sushma Honnavara Prasad, Pora...
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    ISVLSI
    2007
    IEEE
    126views VLSI» more  ISVLSI 2007»
    MOTIM - A Scalable Architecture for Ethernet Switches
    15 years 6 months ago
    MOTIM - A Scalable Architecture for Ethernet Switches
    Download  www.inf.pucrs.br
    Erico Bastos, Everton Carara, Daniel V. Pigatto, N...
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    CCCG
    2009
    115views Computational Geometry» more  CCCG 2009»
    Data Structures for Reporting Extension Violations in a Query Range
    15 years 24 days ago
    Data Structures for Reporting Extension Violations in a Query Range
    Download  cccg.ca
    Design Rule Checking (DRC) in VLSI design involves checking if a given VLSI layout satisfies a given set of rules, and reporting the violations if any. We propose data structures ...
    Ananda Swarup Das, Prosenjit Gupta, Kannan Srinath...
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    NIPS
    2003
    119views Information Technology» more  NIPS 2003»
    Minimising Contrastive Divergence in Noisy, Mixed-mode VLSI Neurons
    15 years 1 months ago
    Minimising Contrastive Divergence in Noisy, Mixed-mode VLSI Neurons
    Download  books.nips.cc
    This paper presents VLSI circuits with continuous-valued probabilistic behaviour realized by injecting noise into each computing unit(neuron). Interconnecting the noisy neurons fo...
    Hsin Chen, Patrice Fleury, Alan F. Murray
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