ARITH 1999 - PDF Preprint Papers

ARITH 1999 IEEE Symposium on Computer Arithmetic

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ARITH
1999
IEEE

153views Applied Computing» more ARITH 1999»

Reduced Latency IEEE Floating-Point Standard Adder Architectures

13 years 9 months ago

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The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...

Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...

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Id	Views	Title	Status

1	153	Reduced Latency IEEE Floating-Point Standard Adder Architectures	claim
2	142	Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm	claim
3	134	Correctness Proofs Outline for Newton-Raphson Based Floating-Point Divide and Square Root Algorithms	claim
4	122	Digit-Recurrence Algorithm for Computing Euclidean Norm of a 3-D Vector	claim
5	113	Boosting Very-High Radix Division with Prescaling and Selection by Rounding	claim
6	112	Montgomery Modular Exponentiation on Reconfigurable Hardware	claim
7	112	Floating-Point Unit in Standard Cell Design with 116 Bit Wide Dataflow	claim
8	103	High-Speed Inverse Square Roots	claim
9	100	Number-Theoretic Test Generation for Directed Rounding	claim
10	97	Complex Logarithmic Number System Arithmetic Using High-Radix Redundant CORDIC Algorithms	claim
11	97	Arithmetic with Signed Analog Digits	claim
12	92	The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures	claim
13	90	On Infinitely Precise Rounding for Division, Square Root, Reciprocal and Square Root Reciprocal	claim
14	89	Moduli for Testing Implementations of the RSA Cryptosystem	claim
15	83	On the Design of High-Radix On-Line Division for Long Precision	claim
16	77	Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition	claim
17	76	Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding	claim
18	71	A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication	claim
19	70	New Algorithms for Improved Transcendental Functions on IA-64	claim
20	63	Multiplications of Floating Point Expansions	claim
21	61	Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16	claim
22	57	Necessary and Sufficient Conditions for Parallel, Constant Time Conversion and Addition	claim

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