ARITH   1999 IEEE Symposium on Computer Arithmetic
Wall of Fame | Most Viewed ARITH-1999 Paper
12 years 6 months ago
Reduced Latency IEEE Floating-Point Standard Adder Architectures
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...
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