FCCM 2004 - PDF Preprint Papers

FCCM 2004 Annual IEEE Symposium on Field-Programmable Custom Computing Machines

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FCCM
2004
IEEE

269views VLSI» more FCCM 2004»

FPGA Based Network Intrusion Detection using Content Addressable Memories

13 years 8 months ago

Download snsl.engr.uconn.edu

In this paper, we introduce a novel architecture for a hardware based network intrusion detection system (NIDS). Current software-based NIDS are too compute intensive and can not ...

Long Bu, John A. Chandy

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Id	Views	Title	Status

1	269	FPGA Based Network Intrusion Detection using Content Addressable Memories	claim
2	175	A Flexible Hardware Encoder for Low-Density Parity-Check Codes	claim
3	163	Implementation Results of Bloom Filters for String Matching	claim
4	152	Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor	claim
5	144	Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine	claim
6	143	Reconfigurable Molecular Dynamics Simulator	claim
7	141	Deep Packet Filter with Dedicated Logic and Read Only Memories	claim
8	136	The MOLEN Processor Prototype	claim
9	133	A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs	claim
10	130	Hyperreconfigurable Architectures for Fast Run Time Reconfiguration	claim
11	129	Design Patterns for Reconfigurable Computing	claim
12	121	A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA	claim
13	121	Validation of an Advanced Encryption Standard (AES) IP Core	claim
14	118	Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor	claim
15	112	ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers	claim
16	109	Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs	claim
17	107	An Alternate Wire Database for Xilinx FPGAs	claim
18	103	A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder	claim
19	102	Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications	claim
20	101	Hardware-in-the-Loop Evolution of a 3-bit Multiplier	claim
21	101	Secure Remote Control of Field-programmable Network Devices	claim
22	98	Automated Least-Significant Bit Datapath Optimization for FPGAs	claim
23	97	Unidirectional Switch-Boxes for Synthesizable Reconfigurable Arrays	claim
24	96	Pre-Decoded CAMs for Efficient and High-Speed NIDS Pattern Matching	claim
25	95	An Arithmetic Library and Its Application to the N-body Problem	claim
26	94	A Structured System Methodology for FPGA Based System-on-A-Chip Design	claim
27	91	An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding	claim
28	90	Migrating Functionality from ROMS to Embedded Multipliers	claim
29	89	Word-Length Optimization of Folded Polynomial Evaluation	claim
30	87	A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation	claim

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