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    2008
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    A Java processor architecture for embedded real-time systems
    13 years 4 months ago
    A Java processor architecture for embedded real-time systems
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    Architectural advancements in modern processor designs increase average performance with features such as pipelines, caches, branch prediction, and out-of-order execution. However...
    Martin Schoeberl
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    A Java processor architecture for embedded real-time systems
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    Evaluation and optimization of a peer-to-peer video-on-demand system
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    3Download preprint from source131
    Formal verification of ASMs using MDGs
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    Processor array architectures for flexible approximate string matching
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    Analyzing concurrency in streaming applications
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    6Download preprint from source116
    Analyzing composability of applications on MPSoC platforms
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    7Download preprint from source110
    A model for service-oriented communication systems
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    8Download preprint from source108
    COMPASS - A tool for evaluation of compression strategies for embedded processors
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    A methodology to design arbitrary failure detectors for distributed protocols
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    10Download preprint from source94
    Energy reduction through crosstalk avoidance coding in networks on chip
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    11Download preprint from source91
    Using supplier locality in power-aware interconnects and caches in chip multiprocessors
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    12Download preprint from source81
    Improving stability for peer-to-peer multicast overlays by active measurements
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    13Download preprint from source79
    Memory hierarchy performance measurement of commercial dual-core desktop processors
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    14Download preprint from source74
    Resource conflict detection in simulation of function unit pipelines
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    15Download preprint from source74
    Improving evolutionary exploration to area-time optimization of FPGA designs
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    A novel caching mechanism for peer-to-peer based media-on-demand streaming
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    17Download preprint from source71
    Nash equilibria in bandwidth allocation for non-cooperative peer-to-peer networks
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    18Download preprint from source67
    A low-complexity microprocessor design with speculative pre-execution
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    19Download preprint from source63
    DLL-conscious instruction fetch optimization for SMT processors
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