Implementation of a Content-Scanning Module for an Internet Firewall

A module has been implemented in Field Programmable Gate Array (FPGA) hardware that scans the content of Internet packets at Gigabit/second rates. All of the packet processing operations are performed using reconfigurable hardware within a single Xilinx Virtex XCV2000E FPGA. A set of layered protocol wrappers is used to parse the headers and payloads of packets for Internet protocol data. A content matching server automatically generates the Finite State Machines (FSMs) to search for regular expressions. The complete system is operated on the Field-programmable Port Extender (FPX) platform.

• Type: Conference
• Year: 2003
• Where: FCCM
• Authors: James Moscola, John W. Lockwood, Ronald Prescott Loui, Michael Pachos
• Keywords: FCCM 2003, Field Programmable Gate Array, Hardware, Layered Protocol Wrappers, Virtex XCV2000E FPGA