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13

ISCAS
2003
IEEE

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A high speed low input current low voltage CMOS current comparator

13 years 9 months ago

A high speed low input current low voltage CMOS current comparator

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A new high speed low input current comparator is proposed in this paper. Based on a simple negative feedback scheme around the transimpedance stage with an emphasis on a very large loop-gain, the transformed voltage signal is maintained at the lowest swing that results in a speed improvement. On a 0.25um TSMC CMOS process, simulation results demonstrate propagation delays of 3.6ns with ±100nA input current

K. Moolpho, Jitkasem Ngarmnil, S. Sitjongsataporn

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Input Current Comparator | ISCAS 2003 | Negative Feedback Scheme | TSMC CMOS Process |

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Added	04 Jul 2010
Updated	04 Jul 2010
Type	Conference
Year	2003
Where	ISCAS
Authors	K. Moolpho, Jitkasem Ngarmnil, S. Sitjongsataporn

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