Iterative Symmetry Indices Decomposition for Ternary Logic Synthesis in Three-Dimensional Space

This paper introduces the implementation of the Iterative Symmetry Indices Decomposition (ISID) for the synthesis of ternary threedimensional logic circuits. The synthesis of regular two-dimensional circuits using ISID has been introduced previously, and the synthesis of areaspecific circuits using ISID has been demonstrated. The new method is useful for the synthesis of functions using three-dimensional regular logic circuits whenever volume-specific layout constraints have to be satisfied.

• Type: Conference
• Year: 2003
• Where: ISMVL
• Authors: Anas Al-Rabadi
• Keywords: Artificial Intelligence, ISMVL 2003, Logic Circuits, Regular Two-dimensional Circuits, Threedimensional Logic Circuits