Performance trade-off analysis of analog circuits by normal-boundary intersection

We present a new technique to examine the trade-off regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on circuit simulation, sizing rules, which capture elementary topological and technological constraints, and an advanced multicriteria optimization formulation called normal-boundary intersection. We are able to efficiently calculate a well-balanced discretization of a Pareto surface, identify the active constraints, which prevent a further improvement, and even rank these constraints in terms of stringency. Experimental results demonstrate the efficacy and efficiency of the method and its potential for topology selection and analog synthesis. Categories and Subject Descriptors B.8.2 [Performance and Reliability]: Performance Analysis and Design Aids; B.7.2 [Integrated Circuits]: Design Aids—simulation; I.6.3 [Simulation and Modeling]: Applications; J.6 [Computer-Aided Engineering]: Computer-Aided Design Ge...

• Type: Conference
• Year: 2003
• Where: DAC
• Authors: Guido Stehr, Helmut E. Graeb, Kurt Antreich
• Keywords: Computer Architecture, DAC 2003, Normal-boundary Intersection, Pareto Optimal, Performance