A Simple Low-Energy Instruction Wakeup Mechanism

Instruction issue consumes a large amount of energy in out of order processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hardware complexity to reduce energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a mechanism for instruction wakeup, which uses a multi-block instruction queue design. The blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as

• Type: Conference
• Year: 2003
• Where: ISHPC
• Authors: Marco A. Ramírez, Adrián Cristal, Alexander V. Veidenbaum, Luis Villa, Mateo Valero
• Keywords: Distributed And Parallel Computing, ISHPC 2003, Multi-block Instruction Queue, Problem Require Prediction, Wakeup Logic