Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

10

ISCAS
2002
IEEE

favoriteEmaildiscussreport

97views Hardware» more ISCAS 2002»

A new pipelined adaptive DFE architecture with improved convergence rate

13 years 9 months ago

A new pipelined adaptive DFE architecture with improved convergence rate

Download access.ee.ntu.edu.tw

Meng-Da Yang, An-Yeu Wu

Real-time Traffic

Hardware | ISCAS 2002 |

claim paper

Related Content

» A systolic architecture for LMS adaptive filtering with minimal adaptation delay

» A Multilayer 2D Adaptive Filtering Architecture Based on McClellan Transformation

» P4 A platform for FPGA implementation of protocol boosters

Post Info
More Details (n/a)

Added	15 Jul 2010
Updated	15 Jul 2010
Type	Conference
Year	2002
Where	ISCAS
Authors	Meng-Da Yang, An-Yeu Wu

Comments (0)