On Accommodating Particular Analog System Models with VHDL

In this paper the problem of accommodating particular analog system models, with emphasis on interconnection's representation, with discrete event simulators, and particularly with VHDL circuit descriptions, is discussed and a solution is proposed. The results can be successfully used for VHDL modeling and simulation, but they are implementation independent.

• Type: Conference
• Year: 2000
• Where: BMAS
• Authors: Gabriel Stefan Popescu
• Keywords: BMAS 2000, Discrete Event Simulators, Interconnection's Representation, Modelling And Simulation, VHDL Circuit Descriptions