Representative path selection for post-silicon timing prediction under variability

The identification of speedpaths is required for post-silicon (PS) timing validation, and it is currently becoming timeconsuming due to manufacturing variations. In this paper we propose a method to find a small set of representative paths that can help monitor a large pool of target paths which are more prone to fail the timing at PS stage, to reduce with the validation effort. We first introduce the concept of effective rank to select a small set of representative paths to predict the target paths with high accuracy. To handle the large dimension and degree of independent random parameter variations, we then allow modeling target path delays using segment delays and formulate it as a convex problem. The identification of segments can be incorporated in design of custom test structures to monitor PS circuit timing behavior. Simulations show that we can use the actual timing information of less than 100 paths or segments to accurately predict up to 3,500 target paths (statistica...

• Type: Conference
• Year: 2010
• Where: DAC
• Authors: Lin Xie, Azadeh Davoodi
• Keywords: Computer Architecture, DAC 2010, Representative Paths, Small Set, Target Paths