Impact of PE Mapping on Cray T3E Message-Passing Performance

The aim of this paper is to study the influence of processor mapping on message passing performance of two different parallel computers: the Cray T3E and the SGI Origin 2000. For this purpose, we have first designed an experiment where processors are paired off in a random manner and messages are exchanged between them. In view of the results of this experiment, it is obvious that the physical placement must be accounted for. Consequently, a mapping algorithm for the Cray T3E, suited cartesian topologies is studied. We conclude by making comparisons between our T3E algorithm, the MPI default mapping and another algorithm proposed by M

• Type: Conference
• Year: 2000
• Where: EUROPAR
• Authors: Eduardo Huedo, Manuel Prieto, Ignacio Martín Llorente, Francisco Tirado
• Keywords: Cray T3e, Distributed And Parallel Computing, EUROPAR 2000, Mapping Algorithm, SGI Origin 2000