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CHES
2008
Springer

Power and Fault Analysis Resistance in Hardware through Dynamic Reconfiguration

13 years 7 months ago
Power and Fault Analysis Resistance in Hardware through Dynamic Reconfiguration
Dynamically reconfigurable systems are known to have many advantages such as area and power reduction. The drawbacks of these systems are the reconfiguration delay and the overhead needed to provide reconfigurability. We show that dynamic reconfiguration can also improve the resistance of cryptographic systems against physical attacks. First, we demonstrate how dynamic reconfiguration can realize a range of countermeasures which are standard for software implementations and that were practically not portable to hardware so far. Second, we introduce a new class of countermeasure that, to the best of our knowledge, has not been considered so far. This type of countermeasure provides increased resistance, in particular against fault attacks, by randomly changing the physical location of functional blocks on the chip area at run-time. Third, we show how fault detection can be provided on certain devices with negligible area-overhead. The partial bitstreams can be read back from the reconfi...
Nele Mentens, Benedikt Gierlichs, Ingrid Verbauwhe
Added 12 Oct 2010
Updated 12 Oct 2010
Type Conference
Year 2008
Where CHES
Authors Nele Mentens, Benedikt Gierlichs, Ingrid Verbauwhede
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