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2008

Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs

13 years 5 months ago
Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs
Coarse-grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine for various types of System-on-Chips (SoCs). Interconnection in these architectures is one of the important factors to be evaluated. MuCCRA-1, the first prototype of MuCCRA(MultiCore Configurable Reconfigurable Architecture) project, uses a typical island-style interconnection in its PE array. Although the island-style interconnection is flexible, the large delay time caused by passing multiple switches and long wires often degrades its clock frequency. In this paper, MuCCRA-D, a dynamically reconfigurable processor which uses direct interconnection between neighboring PEs, is designed and evaluated. The evaluation results show that the required semiconductor area for MuCCRA-D is 12% smaller than that of MuCCRA-1 by reducing wiring resource in the interconnection. Since higher clock frequency can be used, DCT, -Blending, Bubble-Sort and SHA-...
Masaru Kato, Yohei Hasegawa, Hideharu Amano
Added 29 Oct 2010
Updated 29 Oct 2010
Type Conference
Year 2008
Where ERSA
Authors Masaru Kato, Yohei Hasegawa, Hideharu Amano
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