Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

5

JOLPE
2006

favoriteEmaildiscussreport

37views more JOLPE 2006»

Transistor Sizing of Logic Gates to Maximize Input Delay Variability

13 years 5 months ago

Transistor Sizing of Logic Gates to Maximize Input Delay Variability

Download www.eng.auburn.edu

Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush

Real-time Traffic

JOLPE 2006 |

claim paper

Related Content

» Design of Variable Input Delay Gates for Low Dynamic Power Circuits

» Variable Input Delay CMOS Logic for Low Power Design

» Delay modeling and static timing analysis for MTCMOS circuits

» Path Delay Estimation using Power Supply Transient Signals A Comparative Study using Fouri...

» Minimization of the expected path length in BDDs based on local changes

» Optimization techniques for highperformance digital circuits

Post Info
More Details (n/a)

Added	13 Dec 2010
Updated	13 Dec 2010
Type	Journal
Year	2006
Where	JOLPE
Authors	Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell

Comments (0)