Enhancing timing-driven FPGA placement for pipelined netlists

FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a fundamentally different problem to the CAD tools, limiting the benefit of these techniques. In this paper we discuss some of the inherent quality and runtime issues pipelined netlists present to existing timingdriven placement approaches. We then present some algorithmic modifications that reduce post-compilation critical path delay by an average of 40%. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids ? Placement and routing. General Terms Algorithms, Design. Keywords Reconfigurable logic, FPGA, placement, simulated annealing, timing-driven, pipelined.

• Type: Conference
• Year: 2008
• Where: DAC
• Authors: Kenneth Eguro, Scott Hauck
• Keywords: DAC 2008, Design Automation, FPGA Application Developers, Issues Pipelined Netlists, Registered Netlists