Low-Floor Detection/Decoding of LDPC-Coded Partial Response Channels

Abstract— There is a well-known error-floor phenomenon associated with iterative LDPC decoders which has delayed the use of LDPC codes in certain communication and storage systems. Error floors are known to generally be caused by so-called trapping sets, subsets of code bits which induce a subgraph in a code’s Tanner graph that have the effect of locking up the decoder. In earlier work, the authors proposed three decoderbased techniques that lower the LDPC error floors on binaryinput AWGN channels. In this paper, we introduce two techniques that lower the error-rate floors for LDPC-coded partial response (PR) channels, which are applicable to magnetic and optical storage. The techniques involve, via external measures, “pinning” one of the bits in each problematic trapping set and then letting the iterative decoder proceed to correct the rest of the bits. We present two classes of pinning solutions: (1) a pre-pinning technique which fixes (pins) selected trapping set bits p...

• Type: Journal
• Year: 2010
• Where: JSAC
• Authors: Yang Han, William E. Ryan
• Keywords: Decoders, JSAC 2010, Ldpc Code, Trapping Set