DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior

Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to the worst-case conditions to guarantee error-free computation but may also lead to very inefficient designs. Recently, there are processor works that over-clock the chip to achieve higher performance to the point where timing errors occur, and then error correction is performed either through circuit-level or microarchitecture-level techniques. This approach in general is referred to as Timing Speculation. In this paper, we propose a new circuit optimization technique "DynaTune" for timing speculation based on the dynamic behavior of a circuit. DynaTune optimizes the most dynamically critical gates of a circuit and improves the circuit's throughput under a fixed power budget. We test this proposed technique with two timing speculation schemes - Telescopic Unit (TU) and Razor Logic (RZ). Experim...

• Type: Journal
• Year: 2009
• Where: ICCAD
• Authors: Lu Wan, Deming Chen
• Keywords: Design, Hardware, ICCAD 2009, Throughput, Timing Speculation