Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint

We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. In contrast to prior work, we consider the pre-bond test-pin-count constraint during optimization since these pins occupy large silicon area that cannot be used in functional mode. In addition, the proposed test-architecture design takes the SoC layout into consideration and facilitates the sharing of test wires between pre-bond tests and post-bond test, which significantly reduces the routing cost for a test-access mechanism in 3D technology. Experimental results for the ITC'02 SoC benchmarks circuits demonstrate the effectiveness of the proposed solution.

• Type: Journal
• Year: 2009
• Where: ICCAD
• Authors: Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. Mak
• Keywords: Hardware, ICCAD 2009, Large Silicon Area, Pre-bond Test-pin-count Constraint, Test-architecture Design