Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines

—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-chip caches, it is important to protect these SRAM structures against lifetime and manufacture-time failures. Designers typically over-provision caches with additional resources to overcome hard-faults. However, static allocation and binding of redundant spares results in low utilization of the extra resources and ultimately limits the number of defects that can be tolerated. This work re-examines the design of process variation tolerant on-chip caches with a focus on providing the flexibility and dynamic reconfigurability necessary to tolerate large numbers of defects with modest hardware overhead. Our approach, ZerehCache, virtually reorganizes the cache data array using a permutation network to provide more degrees of freedom for spare allocation. A graph coloring algorithm is used to configure the netw...

• Type: Journal
• Year: 2011
• Where: TC
• Authors: Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke
• Keywords: Designs, On-chip Caches, Pareto Optimal Zerehcaches, Software Engineering, TC 2011