An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV

Abstract Fractional Motion Estimation (FME) in highdefinition H.264 presents a significant design challenge in terms of memory bandwidth, latency and area cost as there are various modes and complex mode decision flow, which require over 45% of the computation complexity in the H.264 encoding process. In this paper, a new highperformance VLSI architecture for Fractional Motion Estimation (FME) in H.264/AVC based on the full-search algorithm is presented. This architecture is made up of three different pipeline processors to establish a trade-off between processing time and hardware utilization. The computing scheme based on a 4-pixel interpolation unit with a 10-pixel input bandwidth is capable of processing a macroblock (MB) in 870 clock cycles. The final VLSI

• Type: Journal
• Year: 2011
• Where: VLSISP
• Authors: Gustavo A. Ruiz, Juan A. Michell
• Keywords: Abstract Fractional Motion, Database, Fractional Motion Estimation, Mode Decision Flow, VLSISP 2011