A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network

This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedded applications that have a high degree of task-level parallelism among computational kernels. The test chip was fabricated in 65nm CMOS consisting of 164 simple small programmable cores, three dedicated-purpose accelerators and three shared memory modules. All processors are clocked by their own local oscillators and communication is achieved through a simple yet effective source-synchronous communication technique that allows each interconnection link between any two processors to sustain a peak throughput of one data word per cycle. A complete 802.11a WLAN baseband receiver was implemented on this platform. It has a real-time throughput of 54 Mbps with all processors running at 594 MHz and 0.95 V, and consumes an average 174.76 mW with 12.18 mW (or 7.0%) dissipated by its interconnection links. We can full...

• Type: Conference
• Year: 2009
• Where: NOCS
• Authors: Anh T. Tran, Dean Truong, Bevan M. Baas
• Keywords: Circuit-switched On-chip Network, Computer Networks, Heterogeneous Computational Platform, Interconnection Links, NOCS 2009