Low Energy Tree Based Network on Chip Architectures Using Homogeneous Routers for Bandwidth and Latency Constrained Multimedia A

Abstract— Design of Network on chip architectures for multimedia applications is being widely studied. This involves design decisions at various levels of hierarchy. Topology design is one of the significant factors that affect the net delay and the energy consumption of the system. Most of the applications are characterized by bandwidth requirements and latency constraints. The topology must be built satisfying these constraints. The paper aims in generating low energy tree based topologies using homogeneous routers for bandwidth and latency constrained applications.

• Type: Conference
• Year: 2009
• Where: ICETET
• Authors: Deepak Majeti, Aditya Pasalapudi, Kishore Yalamanchili
• Keywords: Emerging Technology, ICETET 2009, Latency Constrained Applications, Latency Constraints, Topology Design