Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits

A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approach is compared with two other techniques based on conventional methods used for 2-D interconnects. Simulation results show that the proposed approach decreases the total wire delay up to 42% as compared to conventional approaches. The complexity of the proposed algorithm is linear to the number of planes that the wire spans. Key words: 3-D ICs, repeater insertion, on-chip interconnect, timing optimization

• Type: Conference
• Year: 2009
• Where: NANONET
• Authors: Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli
• Keywords: 2-D Interconnects, 3-D Interconnects, Chemistry, NANONET 2009, Repeater