Compiling for vector-thread architectures

Vector-thread (VT) architectures exploit multiple forms of parallelism simultaneously. This paper describes a compiler for the Scale VT architecture, which takes advantage of the VT features. We focus on compiling loops, and show how the compiler can transform code that poses difficulties for traditional vector or VLIW processors, such as loops with internal control flow or cross-iteration dependences, while still taking advantage of features not supported by multithreaded designs, such as vector memory instructions. We evaluate the compiler using several embedded benchmarks and show that we can obtain substantial speedups over a single-issue, in-order scalar machine. Categories and Subject Descriptors

• Type: Conference
• Year: 2008
• Where: CGO
• Authors: Mark Hampton, Krste Asanovic
• Keywords: CGO 2008, Compiler, Scale VT Architecture, Software Engineering, VT Features