Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming

Multi-input addition is an important operation for many DSP and video processing applications. On FPGAs, multi-input addition has traditionally been implemented using trees of carry-propagate adders. This approach has been used because the traditional lookup table (LUT) structure of FPGAs is not amenable to compressor trees, which are used to implement multi-input addition and parallel multiplication in ASIC technology. In prior work, we developed a greedy heuristic method to map compressor trees onto the general logic of an FPGA using a component called generalized parallel counter (GPC). Although this technique reduced the combinational delay of our circuits, when synthesized onto Altera Stratix-II FPGAs, by 27% on average; however, the area was increased by an average 11%. To further reduce the delay and limit the increase in area, we have developed a new solution to the mapping problem based on integer linear programming. This new approach reduced the delay of the compressor tree ...

• Type: Conference
• Year: 2008
• Where: DATE
• Authors: Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
• Keywords: Altera Stratix-II FPGAs, Compressor Tree, DATE 2008, Hardware, Multi-input Addition