0/1 Knapsack on Hardware: A Complete Solution

We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was intentionally selected because its dynamic dependencies introduce difficulties in hardware implementation. The architecture uses a divide-and-conquer technique that results in a pseudo-linear memory requirement. This memory reduction comes in exchange for a factor of two slowdown due to redundant computation. The architecture uses Θ(n + p(C + Wmax)) memory and the run time is Θ(nC/p + nlog(n/p)). The heart of the architecture is a systolic module to compute the optimal profit for any problem that fits in available hardware resources. We implemented the module using 64 processors on an Alpha Data coprocessor board using a Xilinx VirtexII FPGA(2001 technology). Our implementation showed a factor of 32 improvement on the total execution time over a sequential al

• Type: Conference
• Year: 2007
• Where: ASAP
• Authors: K. Nibbelink, S. Rajopadhye, R. McConnell
• Keywords: Architecture, ASAP 2007, Distributed And Parallel Computing, Dynamic Programming Problem, Pseudo-linear Memory Requirement