Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508

This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the IEC 61508, an international norm for the functional safety of electronic safety-related systems, of which an overview is given in the paper. The methodology is based on a theory to decompose a digital circuit in “sensible zones” and a tool that automatically extracts these sensible zones from the RTL description. It includes as well a spreadsheet to compute the metrics required by the IEC norm such Diagnostic Coverage and Safe Failure Fraction. The FMEA results are validated by using another tool suite including a fault injection environment. The paper explains how to take benefits of the information provided by such approach and as example it is described how the methodology has been applied to design memory sub-systems to be used in fault robust microcontrollers for automotive applications. This method...

• Type: Conference
• Year: 2007
• Where: DATE
• Authors: Riccardo Mariani, Gabriele Boschi, Federico Colucci
• Keywords: DATE 2007, Hardware, IEC 61508, Methodology, Safe Failure Fraction