A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit

—this paper reports a PFD/CP linearization technique and a new charge pump circuit to enhance the performance of a delta-sigma (∆Σ) fractional-N PLL. The proposed method improves the PLL linearity by forcing the PFD/CP to operate in a linear part of its transfer characteristic; while the CP circuit minimizes the current mismatch between the up and down currents by feedback. These circuit techniques are employed in the design of a 2.4-GHz ∆Σ fractional-N PLL. This chip has been fabricated in the TSMC 0.18-µm CMOS process. The experimental results demonstrate that the proposed techniques considerably improve the fractional-N PLL performance. This

• Type: Conference
• Year: 2008
• Where: ISCAS
• Authors: Ching-Lung Ti, Yao-Hong Liu, Tsung-Hsien Lin
• Keywords: Fractional-n Pll, Hardware, ISCAS 2008, PLL Linearity, ∆Σ Fractional-n Pll