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An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems

9 years 3 months ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and redesign a system to reach near an optimal value. The resulting effect is a long design time. In this paper, we introduce an effective scheme that accelerates design. A system-level pruning of design exploration space speeds up the optimization process. Through a single-pass simulation for a reference customization and a model for estimating and evaluating the system’s performance, pruning of design space is achieved. Experimental results show that a substantial reduction in design time is possible. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles; B.7.2 [Integrated Circuits]: Design Aids; C.3 [Specialpurpose and Application-based Systems]; C.5.4 [Integrated Circuits]: Computer System Implementation—VLSI systems; D.3.2 [Programming Languages]: Language Classificati...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
Added 15 Jul 2010
Updated 15 Jul 2010
Type Conference
Year 2002
Where ISSS
Authors Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
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