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2007

Accelerated Packet Placement Architecture for Parallel Shared Memory Routers

8 years 11 months ago
Accelerated Packet Placement Architecture for Parallel Shared Memory Routers
Abstract. Parallel shared memory (PSM) routers represent an architectural approach for addressing the high memory bandwidth requirements dictated by output-queued switches. A fundamental related challenge pertains to the design of the high-speed memory management algorithm which is responsible for placing arriving packets into non-conflicting memories. In previous work, we have extended PSM results by introducing the concept of Fabric on a Chip (FoC). The latter advocates the consolidation of core packet switching functions on a single chip. This paper further develops the underlying technology for high-capacity FoC designs by incorporating a speedup factor coupled with a multiple packet placement process. This yields a substantial reduction in the overall memory requirements, paving the way for the implementation of large scale FoCs. We further provide analysis for establishing an upper bound on the sufficient number of memories along with a description of an 80Gbps switch implementa...
Brad Matthews, Itamar Elhanany, Vahid Tabatabaee
Added 30 Oct 2010
Updated 30 Oct 2010
Type Conference
Year 2007
Where NETWORKING
Authors Brad Matthews, Itamar Elhanany, Vahid Tabatabaee
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