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CDES
2006

An Algorithm for Yield Improvement via Local Positioning and Resizing

9 years 1 months ago
An Algorithm for Yield Improvement via Local Positioning and Resizing
The ability to improve the yield of integrated circuits through layout modification has been recognized and several techniques for yield enhanced routing and compaction have been developed. The approach described in this paper is aimed to improve the random defect limited yield of the VLSI design. The goal is achieved by increasing the design tolerance to short (extra material) and open (missing material) type defects. This approach and the suggested algorithm can be used as a post place and route step for improving catastrophic yield loss caused by the random defects. Keywords Yield, layout optimization, yield improvement.
Vazgen Karapetyan
Added 30 Oct 2010
Updated 30 Oct 2010
Type Conference
Year 2006
Where CDES
Authors Vazgen Karapetyan
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