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CDES
2009
170views Hardware» more  CDES 2009»
11 years 27 days ago
Benchmarking GPU Devices with N-Body Simulations
Recent developments in processing devices such as graphical processing units and multi-core systems offer opportunities to make use of parallel techniques at the chip level to obt...
Daniel P. Playne, Mitchell Johnson, Kenneth A. Haw...
CDES
2009
87views Hardware» more  CDES 2009»
11 years 27 days ago
Delay-Insensitive Ternary Logic
This paper develops a delay-insensitive (DI) digital design paradigm that utilizes ternary logic as an alternative to dual-rail logic for encoding the DATA and NULL states. This ne...
Ravi Sankar Parameswaran Nair, Scott C. Smith, Jia...
CDES
2006
118views Hardware» more  CDES 2006»
11 years 1 months ago
Improving the System Performance by a Dynamic File Prediction Model
As the speed gap between CPU and I/O is getting wider and wider, I/O latency plays a more important role to the overall system performance than it used to be. Prefetching consecut...
Tsozen Yeh, Joseph Arul, Kuo-Hsin Tien, I-Fan Chen...
CDES
2006
89views Hardware» more  CDES 2006»
11 years 1 months ago
Autonomous Instruction Memory Equipped with Dynamic Branch Handling Capability
Memory accesses have always been a speed-limiting factor, and memory bandwidth has always been an intensively contended scarce resource. Nevertheless, with recent pervasive emergen...
Hui-Chin Yang, Chung-Ping Chung
CDES
2006
184views Hardware» more  CDES 2006»
11 years 1 months ago
Compilation for Future Nanocomputer Architectures
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
Thomas P. Way
CDES
2006
99views Hardware» more  CDES 2006»
11 years 1 months ago
Teraflop Computing for Nanoscience
: Over the last three decades there has been significant progress in the first principles methods for calculating the properties of materials at the quantum level. They have largel...
Yang Wang 0008, G. M. Stocks, Aurelian Rusanu, D. ...
CDES
2006
108views Hardware» more  CDES 2006»
11 years 1 months ago
RHT: A Context-Based Return Address Predictor
Mohamed M. Zahran, Manoj Franklin
CDES
2006
98views Hardware» more  CDES 2006»
11 years 1 months ago
Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer
Recently, several loop buffer designs have been proposed to reduce instruction fetch energy due to size and location advantage of loop buffer. Nevertheless, on design complexity di...
Bin-Hua Tein, I-Wei Wu, Chung-Ping Chung
CDES
2006
97views Hardware» more  CDES 2006»
11 years 1 months ago
Protein Secondary Structure Prediction Accuracy versus Reduction Methods
Predicting protein secondary structure is a key step in determining the 3D structure of a protein that determines its function. The Dictionary of Secondary Structure of Proteins (...
Saad Osman Abdalla Subair, Safaai Deris
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