Sciweavers

Share
IPPS
2005
IEEE

Analysis of Hardware Acceleration in Reconfigurable Embedded Systems

9 years 8 months ago
Analysis of Hardware Acceleration in Reconfigurable Embedded Systems
Embedded designers now have the capability of offloading software routines into custom applicationspecific hardware blocks. This paper evaluates a domain-specific design system for configurable computing platforms that combine processors and configurable fabrics. Although the proposed work uses floating-point and communication primitives as the specific domain tasks evaluated, the reconfigurable computing platform and the design challenges addressed will become increasingly common in a number of embedded system environments. This paper explores the added cost of hardware resources, area, and power of moving software library routines into hardware blocks in a configurable embedded system based on the MicroBlaze soft processor.
Matthew Ouellette, Daniel A. Connors
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where IPPS
Authors Matthew Ouellette, Daniel A. Connors
Comments (0)
books