Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems

In this paper, we propose a method for speeding-up applications by partitioning them between the reconfigurable hardware blocks of different granularity and mapping critical parts of applications on the coarse-grain reconfigurable hardware. The partitioning method consists of four steps; the Intermediate Representation creation, the kernel identification, the mapping onto coarse-grain reconfigurable blocks, and the mapping onto the FPGA hardware. The method is validated using five real-world applications, where the speedup relative to an all

• Type: Conference
• Year: 2005
• Where: FCCM
• Authors: Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
• Keywords: Coarse-grain Reconfigurable Hardware, FCCM 2005, Hardware, Reconfigurable Hardware, Reconfigurable Hardware Blocks