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EVOW
2008
Springer

Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures

8 years 11 months ago
Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures
Abstract. In this paper we propose three small instances of a reconfigurable circuit and analyze their properties using the brute force method and evolutionary algorithm. Although proposed circuits are very similar, significant differences were demonstrated, namely in the number of unique designs they can implement, the sensitiveness of functions to the inversions in the configuration bitstream and the average number of generations needed to find a target function. These findings are quite unintuitive. Once important (sensitive) bits of the reconfigurable circuit are identified, evolutionary algorithm can incorporate this knowledge. We believe that the proposed type of analysis can help those designers who develop new reconfigurable circuits for evolvable hardware applications.
Lukás Sekanina, Petr Mikusek
Added 19 Oct 2010
Updated 19 Oct 2010
Type Conference
Year 2008
Where EVOW
Authors Lukás Sekanina, Petr Mikusek
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