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2006

A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems

8 years 8 months ago
A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity and mapping critical parts of applications on coarse-grain reconfigurable hardware. The reconfigurable hardware blocks are embedded in a heterogeneous reconfigurable system architecture. The fine-grain part is implemented by an embedded FPGA unit, while for the coarse-grain reconfigurable hardware our developed high-performance coarse-grain data-path is used. The design flow mainly consists of three steps; the analysis procedure, the mapping onto coarse-grain blocks, and the mapping onto the fine-grain hardware. In this work, the methodology is validated using five real-life applications; an OFDM transmitter, a medical imaging technique, a wavelet-based image compressor, a video compression scheme and a JPEG encoder. The experimental results show that the speedup, relative to an all-FPGA solution,
Michalis D. Galanis, Athanasios Milidonis, Athanas
Added 14 Dec 2010
Updated 14 Dec 2010
Type Journal
Year 2006
Where MJ
Authors Michalis D. Galanis, Athanasios Milidonis, Athanasios Kakarountas, Costas E. Goutis
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