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SIGCOMM
1996
ACM

Analysis of Techniques to Improve Protocol Processing Latency

10 years 6 months ago
Analysis of Techniques to Improve Protocol Processing Latency
This paper describes several techniques designed to improve protocol latency, and reports on their effectiveness when measured on a modern RISC machine employing the DEC Alpha processor. We found that the memory system--which has long been known to dominate network throughput--is also a key factor in protocol latency. As a result, improving instruction cache effectiveness can greatly reduce protocol processing overheads. An important metric in this context is the memory cycles per instructions (mCPI), which is the average number of cycles that an instruction stalls waiting for a memory access to complete. The techniques presented in
David Mosberger, Larry L. Peterson, Patrick G. Bri
Added 08 Aug 2010
Updated 08 Aug 2010
Type Conference
Year 1996
Where SIGCOMM
Authors David Mosberger, Larry L. Peterson, Patrick G. Bridges, Sean W. O'Malley
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