Network Simplicity for Latency Insensitive Cores

In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asynchronous. These types of cores provide native flow control that is compatible with this network, thus reducing adapter overhead and buffering needs by applying backpressure directly to the sending core. We show that under realistic traffic patterns our sample network meets performance requirements and uses less power compared to a similar design. This concept of a simplified network, along with latency insensitive cores lends itself well to meeting the needs of low-power interconnect components in future design processes. Traffic patterns of some system-on-chips (SoCs) are known at design time. In these cases, a custom generated network topology and physical placement of components yields improved performance and power than a regular-pattern network [1]. In many embedded applications, absolute performanc...

• Type: Conference
• Year: 2008
• Where: NOCS
• Authors: Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth S. Stevens
• Keywords: Computer Networks, Latency Insensitive Cores, Latency Insensitive Network, Li Protocol, NOCS 2008